1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a semiconductor substrate having an interconnection layer formed thereon.
2. Background Art
In recent years, progress has been made in increasing the number of interconnection layers to be stacked on a semiconductor substrate for increasing the packing density of semiconductor elements. In relation to an ordinary multilayer interconnection, there has often been adopted a device structure which does not involve placement of a dummy pattern at the time of patterning of a first (bottom) layer of metal interconnection.
However, in the case of a semiconductor device having no dummy pattern to be formed on a first metal interconnection layer, a second metal interconnection layer is formed on the first metal interconnection layer by way of an interlayer dielectric film. The semiconductor device may encounter a problem of deteriorated coverage of the second metal interconnection layer in accordance with the density of the first metal interconnection pattern which is to serve as a base material or with the layout of lines or spaces.
FIG. 6 is a schematic cross-sectional view showing a state wherein an interconnection dielectric film 102 is formed on a semiconductor substrate 101; wherein, after a first metal interconnection layer 103 has been formed on the interconnection dielectric film 102, a second interconnection dielectric film 104, an SOG (spin-on-glass) film 105, and a third interconnection dielectric film 106 are formed, in this order, on the first metal interconnection layer 103; and wherein a second metal interconnection layer 107 is formed on the third interconnection dielectric film 106.
In the case of a multilayer interconnection structure, the SOG film 105 to be used for smoothing the second and subsequent layers of metal interconnection and the second and subsequent interconnection dielectric films is spin-coated over the substrate, and the surface of the SOG film 105 is smoothed. The third interconnection dielectric film 106 is formed on the thus-smoothed SOG film 105.
As shown in FIG. 6, the two metal interconnections 103 provided as the first layer are isolated. When the two metal interconnection patterns 103 are spaced apart from each other by, e.g., 0.8 to 1.5 μm or thereabouts, the SOG film 105 to be applied by a spin coater cannot sufficiently enter the space therebetween. For this reason, there arises a problem of the smoothness of the surface of the SOG film 105 being deteriorated. Since the two metal interconnections 103 are isolated, the amount of SOG film 105 supplied becomes deficient, and entry of the SOG film 105 into the space therebetween becomes deteriorated.
As shown in FIG. 6, if a second metal interconnection layer is formed by means of etching while the coverage of the spaces by the SOG film 105 remains deteriorated and if the second metal interconnection layer 107 is formed through etching, residues 107′ of the second metal interconnection layer are produced in portions of a step into which the SOG film 105 has entered poorly. In the worst case, a short circuit arises in the second metal interconnection layer 107.
In order to prevent generation of the etch residues 107′, there has already been known a method of uniformly placing a dummy metal pattern in addition to the first metal interconnection layer 103. FIG. 7 shows an example in which a dummy pattern 108 is formed in the same level as that in which the first metal interconnection layer 103 has been formed, so as to become close thereto. Addition of the dummy pattern 108 prevents isolation of the first metal interconnection layers 103, thus preventing generation of the etch residues 107′ in the space.
When the dummy pattern 108 is added to the first metal interconnection layer 103, a redundant interconnection capacitance arises between the first metal interconnection layer 103 and the dummy pattern 108, thus adversely affecting the operating speed of the device.